1. Field of the Invention
The present invention relates to a switching device of a liquid crystal display device, and particularly, to a liquid crystal display device including a thin film transistor having a single-direction channel.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) is an image display device which is able to display desired information by supplying data signals to pixels arranged in a matrix form according to information, and controls arrangement of the liquid crystal by an electric field.
Typically, the LCD includes: a liquid crystal panel on which unit pixels are arranged in a matrix form and integrated circuits (IC) for driving a liquid crystal. The liquid crystal panel further includes a color filter substrate and a thin film transistor (TFT) array substrate, and the liquid crystal is filled in space between the color filter substrate and the TFT array substrate.
In addition, on the TFT array substrate of the liquid crystal panel, a plurality of data lines for transmitting data signals supplied from data driver ICs toward the unit pixels and a plurality of gate lines for transmitting scan signals supplied from gate driver ICs to the unit pixels are crossed with each other in a right angle, and the unit pixels are defined on the crossed portions of the data lines and the gate lines. The gate driver ICs supply the scan signals sequentially to the plurality of gate lines to activate the unit pixels one by one sequentially, and the data signals are supplied to the unit pixels of an activated line from the data driver ICs.
On the other hand, a common electrode and a pixel electrode are formed on the color filter substrate and the TFT array substrate respectively facing each other to apply an electric field to the liquid crystal. The pixel electrode is formed on the TFT array substrate by unit pixels, while the common electrode is formed on the entire surface of the color filter substrate. Therefore, light transmittance of the liquid crystal cells can be controlled independently by controlling the voltage applied to each of the pixel electrodes.
As described above, in order to control the voltage applied to each of the pixel electrodes, a TFT is formed on each of the liquid crystal cells as a switching device.
The components of the above LCD will be described in detail with reference to the accompanying figures.
FIG. 1 is a plane view showing a unit pixel of a general LCD. Referring to FIG. 1, gate lines 4 are arranged on a substrate in a row direction apart from each other, and data lines 2 are arranged in a column direction apart from each other. A unit pixel is defined on every crossed portions of the data line 2 and of the gate line 4, and comprises a TFT and a pixel electrode 14. A gate electrode 10 of the TFT is formed as extended from a predetermined position of the gate line 4, and a source electrode 8, of which some part is overlapped with the gate electrode 10, is extended from the data line 2. In addition, a drain electrode 12 is formed on a position corresponding to the source electrode 8, and the pixel electrode 14 is electrically contacted with the drain electrode through a drain contact hole 16 formed on the drain electrode 12. The thin film transistor (TFT) comprises a semiconductor layer (not shown) for forming a conductive channel between the source electrode 8 and the drain electrode 12 when the scan signals are supplied to the gate electrode 10 through the gate line 4.
As described above, as the TFT forms the conductive channel between the source electrode 8 and the drain electrode 12 in response to the scan signals supplied from the gate line 4, the data signals supplied to the source electrode 8 through the data line 2 are transmitted to the drain electrode 12.
The pixel electrode 14 connected to the drain electrode 12 through the drain contact hole 16 is made of a transparent material, such as Indium Tin Oxide (ITO). At that time, the pixel electrode 14 generates an electric field on the liquid crystal layer in association with a common transparent electrode (not shown) formed on the color filter substrate in accordance with the data signals supplied from the drain electrode 12.
When the electric field is applied to the liquid crystal layer as described above, the liquid crystal molecules rotate due to dielectric anisotropy to transmit the light emitted from a backlight toward the color filter substrate through the pixel electrode 14, and the amount of the transmitted light is controlled by the amount of the voltage of the data signals.
In addition, a storage electrode 20 connected to the pixel electrode 14 through a storage contact hole 22 is deposited on the gate line 4 to form a storage capacitor 18, and a gate insulating layer (not shown) which is deposited during the forming process of the TFT is formed between the storage electrode 20 and the gate line 4. The storage capacitor 18 is to maintain operation of liquid crystal by charging voltage during the turned-on period of the TFT when the scan signal is applied to the gate line 4 and by supplying the charged voltage to the pixel electrode 14 during the turned-off period of the TFT.
FIG. 2 is a cross sectional view of a unit pixel taken along a line I–I′ in FIG. 1, and includes a color filter substrate 60 facing the TFT array substrate 50 and attached with it; a spacer 70 separating the TFT array substrate 50 from the color filter substrate 60 with a predetermined distance therebetween; and a liquid crystal layer 80 which is the liquid crystal filled in the separated space between the TFT array substrate 50 and the color filter substrate 60.
The TFT (T), the switching device, and the storage capacitor (C) are formed on the TFT array substrate. The TFT is an essential device for driving the liquid crystal and is fabricated in a process using five masks presently.
The process using five masks will be described with reference to FIG. 3 as follows. FIGS. 3A˜3E are views illustrating the processes for fabricating the TFT using the 5 masks.
First, as shown in FIG. 3A, an electrode material 302 for forming a gate line is formed on a glass substrate 301. The electrode material for forming the gate line is generally a metal layer, and also functions as lines on a storing area for maintaining a voltage for a predetermined time and as a gate pad unit.
After forming the gate metal layer, a photoresist (not shown) is deposited on the metal layer, and a photolithography process is performed using a first mask (not shown) to form selectively a channel area, a storing area and a gate pad unit pattern 302 on the glass substrate 301.
Next, as shown in FIG. 3B, a gate insulating layer 303 of SiNx, an active layer 304 and a conductive layer 305 are formed sequentially on the substrate. Then, a photolithography process is performed using a second mask (not shown) to etch the active layer 304 and the conductive layer 305 selectively so that the active layer 304 is defined as the channel area. At that time, the active layer 304 is formed by depositing amorphous silicon (a-Si) and a high doped n-type layer. Plasma enhanced chemical vapor deposition (PECVD) method is generally used to deposit the insulating layer (SiNx) and the active layer.
Next, as shown in FIG. 3C, a photoresist (not shown) is coated on the conductive layer 305 and then, a photolithography process is performed using a third mask (not shown). As a result of the above process, a part of the conductive layer 305 on an active area on which a channel of the TFT is formed is removed and the source/drain electrodes 306 and 307 are defined. Also, a portion of the conductive layer 305 is selectively etched so as to form a data pad unit through which the data signal is applied to the TFT.
Next, as shown in FIG. 3D, a passivation layer 308 is formed on the resultant surface, and then, a photolithography process is performed using a fourth mask (not shown) to selectively etch the passivation layer 308 so as to expose a part of the drain electrode 307 to form a contact hole.
Next, as shown in FIG. 3E, an electrode material is formed on the resultant surface, and a photolithography process is performed using a fifth mask (not shown) to form a pixel electrode 309 connected to the drain electrode 307.
The number of masks is an important factor for fabricating the LCD, and affects directly to the cost or productivity. Therefore, a fabrication method of the LCD using 4 masks has been suggested. In the process of fabricating the TFT using the four masks, it is important to form a half tone photoresist having different thickness by exposing differently depending on the positions of the TFT using a slit mask.
The related art slit mask structure will be described with reference to FIG. 4A. The slit mask comprises a source pattern unit 401 formed as ‘U’ shape to increase a channel length shown in FIG. 4A, a drain pattern unit 402 entered into a concave portion of the source pattern unit and separated by a predetermined distance from three sides of the concave portion, and a slit pattern unit 403. The slit pattern unit 403 further includes a horizontal unit 403a formed between the source pattern unit and the drain pattern unit and horizontal with a long side of the drain pattern, a vertical unit 403b which is vertical to the long side of the drain pattern, and a slant unit 403c where the horizontal unit and the vertical unit meet.
In the four-mask TFT process using the slit mask, the interval of slit and the pattern shape are important factors for determining a shape of the channel and accuracy. In the process of fabricating the pattern of the slit mask, the slit pattern must be fabricated in a precise way with a tolerance less than 2 μm. However, as shown in FIG. 4A, since the related art mask is formed as ‘U’ shape with the slant unit where the slit pattern is bent, the pattern interval becomes uneven especially around the slant unit. Even if the intervals between slits in the mask are the same, variation between the horizontal unit and the slant unit is generated due to technical limits of the mask during fabrication.
Generally, the difference between the width of a channel formed by the horizontal unit of the slit pattern and the width of a channel formed by the vertical unit of the channel is within 500 Å, while the difference between the width of the channel formed by the horizontal or vertical units of the slit pattern and the width of the channel formed by the slant unit of the slit pattern is about 2000 Å. FIG. 4B is a scanning electron microscope (SEM) photo showing a shape of an inferior channel due to the accuracy inferiority of the slit mask.